Simulating and verifying the functionalities of a microprocessor design or other integrated circuit design before fabrication (“pre-silicon”) are important steps for ensuring that the fabricated design will perform properly. Industry competition and other factors can pressure researchers and manufacturers to decrease production cycle times. However, pre-silicon simulation and verification of a design can be time-consuming because of the enormous volume of possible testing scenarios (“test-cases”) to explore and the time each test-case can take to simulate.
One aspect of pre-silicon simulation and verification of a microprocessor design involves simulating operations within the memory of the microprocessor, such as fetches from main memory and writes to cache memory. In many of these simulations, one or more memory walking sequences are performed. Modern microprocessor designs typically include mechanisms to perform memory walking sequences in which the microprocessor advances through a target memory, reading one memory location at a time, and potentially performing one or more operations on the entries contained at each of those memory locations. For example, a microprocessor may perform cache walking sequences through a target cache memory, such as cache purge sequences, where the microprocessor reads every cache location in the target cache memory and evicts entries from those cache locations. While memory walking sequences can consume a large number of processor cycles, modern microprocessors are typically capable of performing memory walking sequences quickly on account of their high clock rates.
When conducting pre-silicon simulations of microprocessor designs that include large memories, such as cache or main memories, simulating memory walking sequences through these target memories can consume a large number of simulated processor cycles. However, a simulated microprocessor performing simulated processor cycles is much slower than its hardware counterpart. Conducting pre-silicon simulations to test and verify memory walking sequences and other microprocessor functions that involve their frequent use can therefore take an exceedingly long time, potentially to the extent that the simulations are impracticable to conduct or must be conducted in a limited fashion, both of which risk leaving design problems undiscovered in the pre-silicon stage.
A way to decrease the testing time required to simulate memory walking sequences would be useful.